1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices and, more particularly, to an erasable programmable read-only memory.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, there has been strongly demanded a nonvolatile semiconductor memory having a large data storage capacity for replacing an existing external data storage device such as a magnetic floppy disk drive unit, a fixed disk unit, etc. Although presently available electrically erasable programmable read-only memory devices have a technical merit such that a high-speed and high-reliability data write/read operation can be realized, these memory devices are not improved to obtain a sufficient data storage capacity.
One reason for the above problem is that, in a conventional electrically erasable programmable read-only memory (to be referred to as an "EEPROM" hereinafter), each memory cell for storing 1-bit data is basically constituted by two transistors. With such an arrangement, a cell area on a chip substrate can not be simply decreased without the use of a specialized high-integration element fabrication technique. According to the existing semiconductor fabrication technology, however, such an element fabrication technique is not perfectly established. Even if the specific element fabrication technique is perfectly established, low productivity avoids practical applications of the technique.
Recently, in order to solve the above problem, a specific type of EEPROM having a "NAND cell" structure has been proposed wherein each memory cell is constituted by only one transistor (field effect transistor), and a number of memory cells are connected in series in each array, thereby to remarkably decrease the number of contact portions between the cell array and a corresponding bit line, so that the integration density can be greatly improved.
The presently proposed "NAND cell" type EEPROM, however, suffers from insufficient reliability in a data read operation. More specifically, in the memory of this type, electric charge carriers (e.g., electrons) stored in a floating gate of a transistor of a selected memory cell are discharged to shift its threshold value in the negative-polarity direction, whereby a logic "1" data is stored in the selected memory cell. Electrons are injected into the floating gate of the transistor of the selected memory cell to shift its threshold value in the positive polarity direction, so that a logic "0" data is stored in the selected memory cell. In a typical example, when the logic "1" data is written, the threshold value of the selected memory cell is at least -2 V, and when the logic "0" data is written, the threshold value of the selected memory cell does not exceed +3 V: the difference between these voltages falls within 5 V. Such a small difference between the threshold value causes degradation of the reliability of a data read operation to be described below.
In the EEPROM of this type, when data stored in a desired memory cell is read out, a low or "L" level potential (e.g., 0 volts) is applied to a word line connected to the selected memory cell. In this state, it is detected whether a current is supplied to a NAND cell array including the selected memory cell, thereby to determine whether the logic "1" or "0" data is stored in the memory cell. When the high or "H" level potential is kept applied to non-selected word lines in such a data read cycle, the threshold value of the memory cell which stores the logic "1" data is gradually shifted in the positive-polarity direction. If the difference between the threshold value obtained when the logic "1" data is stored in the memory cell and that when the logic "0" data stored is small, a slight shift of the threshold value causes a decisive read error of the data. The larger the number of read cycles of the EEPROM, the higher the probability of generation of the read error.
In addition, when a large number of write and erase operations of the data are repeated, variations in threshold values of the memory cells are increased. If the threshold value of the erased memory cell is undesirably shifted to be a relatively large value having the positive polarity, the memory cell in the erase state cannot be enabled when the power supply voltage Vcc is used as an "H" level potential to be applied to the non-selected word lines in the following data read mode. This leads to an undesirable increase in the number of read errors of the EEPROM, thus degrading the operation reliability.
A NAND cell type EEPROM has been disclosed in U.S. Pat. No. 4,939,690 (filed Dec. 27, 1998, and patented Jul. 3, 1990) to Momodomi et al. entitled "Electrically Erasable Programmable Read-Only Memory with NAND Cell Structure that suppresses Memory Cell Threshold Voltage Variation" and assigned to the same assignee of the present application. The EEPROM includes an array of rows and columns of memory cell transistors, which are subdivided into a plurality of NAND cell sections each of which includes a predetermined number of series-connected memory cell transistors. Each memory cell transistor has a floating gate for storing charge carriers and an insulated control gate that overlies the floating gate. Each NAND cell section is coupled at its one node to a corresponding one of parallel bit lines through a selection transistor, and is connected at the other node to a source potential Vs by way of a second selection transistor. Each NAND cell section is coupled to parallel word lines at the control gates of the predetermined number of memory cell transistors included therein.
During an erase operation, all the memory cell transistors are erased at a time in such a manner that a high-level potential (20 volts, for example) is applied to the control gates of memory cell transistors while a low-level potential (zero volts, for example) is applied to the control gates of the first and second selection transistors, causing the memory cell array to be electrically disconnected from the bit lines and the source potential Vs. When the EEPROM is set in a data-write (program) mode, a selected NAND cell section is subjected to a selective program operation such that, while the high-level potential is applied to the first and second selection transistors causing them to turn on, the memory cell transistors are sequentially programmed in the reverse order that they are coupled to the corresponding bit line associated therewith, by applying the high-level potential to the gate electrodes of certain non-selected memory cell transistors that are positioned between the first selection transistor and a specific memory cell transistor as presently selected, thus allowing a data voltage to be transferred from the bit line toward the selected memory cell transistor.
The EEPROM may provides significant teachings as to the achievement of an enhanced reliability by eliminating the occurrence of an undesirable variation in the threshold values of the memory cell transistors during a program operation; unfortunately, the device is not provided with a means for improving the reliability during a read operation.